1. Field of the Invention
The invention relates generally to a method of forming a flash memory device and, more particularly, to a method of forming a gate of a flash memory device, wherein the dielectric layer is etched by controlling the recipe during the gate etch process, thereby preventing attack occurring in the active region of the semiconductor substrate.
2. Discussion of Related Art
A flash memory device is a device fabricated by taking the advantages of EPROM having programming and erase characteristics and EEPROM having electrical programming erase characteristics. The flash memory device can realize a storage state of one bit using one transistor and can perform electrically programming and erase operations.
The flash memory cell generally has a vertical lamination type gate structure having a floating gate formed on a silicon substrate. A multi-layer gate structure typically includes one or more tunnel oxide films or dielectric layers, and a control gate formed on or near the floating gate.
The problems of the related art are described below while describing the gate formation method of the flash memory device in the related art.
A tunnel oxide film, a first polysilicon layer for a floating gate, and a nitride film are sequentially formed on a semiconductor substrate.
After a photoresist pattern is formed on the nitride film, the nitride film, the first polysilicon layer, the tunnel oxide film, and a part of the semiconductor substrate are etched using the photoresist pattern as a mask, forming trenches. A gap-fill process is then performed to form a field region and the nitride film is then stripped.
After a cleaning process is carried out, a dielectric layer, a second polysilicon layer for a control gate, a tungsten silicide film, and a hard mask film are formed.
The hard mask film, the tungsten silicide film, and the second polysilicon layer of the active region and the field region are sequentially etched by a gate etch process. The dielectric layer and a part of the gap-filled oxide film of the field region are etched at the same time when the dielectric layer and the first polysilicon layer of the active region are etched.
In this case, the gate etch process is performed in the same chamber called a “DPS poly chamber.” The hard mask film, the tungsten silicide film, and the second polysilicon layer are etched until the dielectric layer is exposed using a high-selectivity recipe against oxide. The etch process of the dielectric layer is performed such that the dielectric layer and the first polysilicon layer have the same ratio using a recipe in which the etch ratio of oxide and polysilicon becomes 1:1.
However, top corners of the semiconductor substrate of the active region are also partially etched while the dielectric layer and a part of the gap-filled oxide film of the field region are etched during the process of etching the dielectric layer of the active region and the field region. Accordingly, there is a problem in that attack is generated at the top corners.